The present invention relates to a semiconductor memory device and to a method of manufacturing the same, a method of manufacturing a vertical MISFET and a vertical MISFET, and a method of manufacturing a semiconductor device and a semiconductor device; and, more particularly, the invention relates to a technology that is effective when applied to a semiconductor memory device having an SRAM (Static Random Access Memory), wherein each of the memory cells is configured using vertical MISFETs.
In an SRAM (Static Random Access Memory) which represents a kind of general-purpose large-capacity semiconductor memory device, a memory cell comprises, for example, four n channel type MISFETs (Metallinsulator-Semiconductor-Field-Effect-Transistors) and two p channel type MISFETs. Since, however, this type of so-called full CMOS (Complementary-Metal-Oxide-Semiconductor) type SRAM has six MISFETs disposed on a major surface of a semiconductor substrate on a plane basis, it is difficult to scale down the memory cell size. Namely, the full CMOS type SRAM, which needs p and n type well regions for forming CMOS and well isolation regions for respectively separating n channel type MISFETs and p channel type MISFETs from one another, presents difficulties in scaling down the memory cell size.